1. Field of the Invention
The present invention relates to semiconductor devices for collectively forming a plurality of semiconductor integrated circuits, and methods of manufacturing a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor device for collectively forming a plurality of semiconductor integrated circuits by providing a self test circuit capable of generating a test signal by itself and testing the operation of a semiconductor integrated circuit, and a method of manufacturing a semiconductor integrated circuit device.
2. Description of the Background Art
As semiconductor integrated circuits, for example, semiconductor memories such as dynamic random access type memories (hereinafter, referred to as DRAMs) are highly integrated, increase in the time for testing the circuit operation and the load applied to testers is accelerated. The increased test time directly raises the manufacturing cost of a semiconductor integrated circuit.
For example, the functions of a semiconductor memory chip are often tested by a large tester after completion of the wafer process or at the shipment stage after packaging. The function test in this case is strictly performed by designating conditions such as a power supply voltage, an ambient temperature, an input signal timing, an operation mode, a data input, and an address.
The test time increases in proportion to the memory capacity even in a simple writing/reading cycle. If the test is to be performed by a large tester, this may raise the chip cost.
Therefore, a test circuit has been provided inside a chip. Instead of supplying a test signal from a tester to each chip, a test signal generated by the built-in test circuit itself is supplied to the internal circuitry of each chip. According to a signal which is output from the internal circuitry, the built-in test circuit itself determines whether the internal circuitry functions well, and externally outputs the determination result. Such an arrangement can substantially reduce tester loads.
However, provision of the test circuit in each semiconductor integrated circuit chip increases the area of each chip and reduces the number of chips which can be manufactured per wafer.
As each semiconductor integrated circuit has higher performance, however, it is desired that a test circuit and an integrated circuit to be tested are closely provided on one substrate to improve the transfer rate of data which is transmitted between the test circuit and the integrated circuit.
In stead of providing a built-in test circuit for each chip, test circuits are provided in chips which are close to a plurality of integrated circuit chips formed on a wafer to test the integrated circuit chips on the same wafer. FIG. 17 shows an integrated circuit assembly having such a construction disclosed in Japanese Patent Laying-Open No. 4-152543.
Referring to FIG. 17, the conventional integrated circuit assembly having a self test function includes an integrated circuit 31 to be tested, and a self test circuit 32 which extracts test data by experimentally operating the integrated circuit. They are on the same substrate and provided side by side in first and second regions 21 and 22 which can be divided by a chip division line 23.
A semiconductor integrated circuit manufacturing process generally employs an exposure device called a stepper. The stepper has a limit in the size of an area which is exposed by one shot of the stepper. For example, the area exposed by one shot includes, in addition to the pattern of a semiconductor integrated circuit to be manufactured, a TEG (Test Elements Group) pattern for the in-line test which monitors the process, and so on. In this case, the area also has a test circuit (self test circuit) pattern. When the process is matured and transferring of the test circuit is to be eliminated, however, mask revision is necessary and it is ineffective.